(I) Field of the Invention
This invention relates to data processing apparatus for processing programs.
(II) Description of the Prior Art
As is well known in the art, data processing apparatus, for example a micro-computer, is used to process a program made up of a series of instructions. The term "instruction" (or an "instruction word") is used herein to mean a code stored in a memory device, and the data processing apparatus reads out such encoded instruction from the memory device, and then decodes the instruction for performing some sort of operation. Every instruction has a specific meaning for the data processing apparatus, and the types of different instruction range from several tens to several hundreds or more. The word length of a fundamental word is specific to a given data processing apparatus and ranges from several bits to several tens of bits or more than 100 bits. The code or bit length of an ordinary instruction is generally equal to the length of its fundamental word. The code length of certain instructions is several times the length of its fundamental word.
Considering data processing apparatus as apparatus including a memory device which stores instructions or data, it can be considered as a large sequence circuit. A sequence circuit may assume various status conditions. More particularly, it contains at least one memory element (a minimum unit of one bit) of some sort such as a memory device or a flip-flop circuit. Where the total number of bits of all memory elements of a data processing apparatus is equal to N the data processing apparatus may be considered to have available 2.sup.N different status conditions where the redundancy is neglected, and a change of status means a change of a status from one of 2.sup.N status conditions to the another status condition.
The term "operation" hereinafter used means such change of status, and a term "operand" generally means an object to be operated when such memory element as a memory device, a register or a flip-flop circuit is operated. In a data processing apparatus which decodes an instruction and then executes an operation, only a portion, that is a specific operand among numerous memory elements has its status changed. In a special case, the operation to be executed is to change the status of a specific operand to have the same status as another operand (assumed to have the same bit length). Such special operation is termed "transfer of data". Of the two operands participating in the transfer, the former is called the "destination", whereas the latter is called the "source". In other words, the contents of a source operand is transferred to a destination operand. The instructions of prior art data processing apparatus belong to either one of the following two types: ##STR1## The operation designator of (I) designates the operation contents of an operand. More particularly, the contents of an operation, such as, transfer of the contents of a first operand to a second operand, or addition of the contents of the first and second operands and then transfer of the result to a third operand or a subtraction, is identified. In the operand designator, an object to be operated is determined. For example, in the transfer instruction described above, as the first operand, a designation is made to select one of a plurality of registers, or to select an input/output device. Where a memory device is to be selected it is necessary to designate an address of that memory device by some means such as directly designating the address with a code inside of the instruction or indirectly designating the address with a register. It may be considered that a code that determines the address is also included in the operand designator. When the operation designator determines the contents of a specific operation, the number of the operands of that operation would be determined. Thus, whether an operand designator designates one operand, or two operands or three operands is determined by the operation designator.
The instruction of the type (II) is a special one of type (I) where no operand designator is included in an instruction code. In this type, however, an operand to be operated is determined automatically. This means that, not only the number of the operands but also the operand itself (object to be operated) are determined solely by the operation designator (although all of the instruction code constitutes an operation designator). An operand may or may not be designated by a programmer. The example described above will now be described with reference to a prior art data processing apparatus, for example a micro-computer. In this example, for the purpose of simplifying the description, it is assumed that the word length of data is 4 bits, and that the length of the address word of a memory device is 12 bits. These word lengths are selected only for the purpose of description, and the embodiment of this invention to be described later will be described with these bit numbers but it should be understood that the invention is not limited to these specific bit numbers.
FIG. 1 illustrates one example of a prior art data processing apparatus which comprises a memory device 1 having a capacity of 4096 instruction words (each comprising a fundamental word having a length of 8 bits) for storing instructions or data. One of the 4096 addressed locations of the memory device 1 is designated by a program counter 2 which is constituted by 12 bits which is equal to the length of an address word. An instruction word in the memory device 1 designated by the program counter 2 is transferred to an instruction register 3 which is constituted by 8 bits equal to an instruction word length. The instruction transferred to the instruction register 3 is decoded by an instruction decoder 4 to produce several tens of control signals SL, SI, SIM, DA, DAA, etc. which are used to control various gate circuits g.sub.1 through g.sub.13 connected between a source and a destination.
The components described above are generally provided for a conventional data processing apparatus, but the components to be described hereinbelow are added for the sake of description. A bus 5 is provided for transferring data between respective operands. The bus 5 consists of 4 bits which is equal to the data word length. There is also provided an accumulator 6 which is constituted by a four bit register and is where most of the instructions of the arithmetic operations and the transfer operations are executed. There is also provided an arithmetic logic unit 7 (usually termed an ALU) which performes arithmetical operations such as addition, and logical operations such as logical product. The output of ALU 7 is fed back to the accumulator 6. For the purpose of identifying whether the result of the operation is a particular result or not, the output terminal of ALU 7 is connected to a flip-flop circuit 8 which is called a status flag. Furthermore, there are provided a memory device 9 which stores only data and registers 10 and 11 (termed H and L) for determining the address of the memory device 9. The memory device 9 has a capacity of 256 words (each word comprises 4 bits) and each one of the 256 addressed locations is designated by both H and L registers 10 and 11 each having 4 bits each (for a total of 8 bits). The memory device 9 and H and L registers 10 and 11 are bidirectionally connected to the bus 5. Each of an input device 12 and an output device 13 comprises a 4 bit register connected to the bus 5. Means 14 is connected to the program counter 2 for incrementing the count value thereof for enabling the counter to read out instructions in a regular order. For an ordinary instruction, the count value of the program counter 2 is incremented by means 14. For the purpose of changing the flow of the program, that is for changing the count value of the program counter 2 by means other than said means, the system is constructed to transfer data to the program counter 2 from the bus 5 and the memory device 1. A stack 15 is bidirectionally connected to the program counter 2 for the purpose of temporarily saving the contents thereof when processing subroutines or interrupts.
Some of the instructions are illstrated as follows:
______________________________________ 1. LA 1010 r.sub.3 r.sub.2 r.sub.1 r.sub.0 A .rarw. r 2. ST 1011 r.sub.3 r.sub.2 r.sub.1 r.sub.0 r .rarw. A 3. LAI 0011 i.sub.3 i.sub.2 i.sub.1 i.sub.0 A .rarw. i.sub.3 i.sub.2 i.sub.1 i.sub.0 4. AAI 0010 i.sub.3 i.sub.2 i.sub.1 i.sub.0 A .rarw. A + i.sub.3 i.sub.2 i.sub.1 i.sub.0 5. ADD 01101 001 A .rarw. A + M 6. AND 01011000 A .rarw. A .LAMBDA. M 7. JMP 1100 a.sub.11 a.sub.10 a.sub.9 PC .rarw. a.sub.11 a.sub.10 a.sub.9 a.sub.8 a.sub.7 a.sub.8 a.sub.7 a.sub.6 a.sub.5 a.sub.4 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 a.sub.1 a.sub.3 a.sub.2 a.sub.1 a.sub.0 a.sub.0 8. CALL 1101 a.sub.11 a.sub.10 a.sub.9 Stack .rarw. Pc + 2 a.sub.8 a.sub.7 a.sub.6 a.sub.5 a.sub.4 PC .rarw. a.sub.11 a.sub.10 a.sub.9 a.sub.8 a.sub.7 a.sub.3 a.sub.2 a.sub.1 a.sub.0 a.sub.6 a.sub.5 a.sub.4 a.sub.3 a.sub.2 a.sub.1 a.sub.0 9. RTN 11110101 PC .rarw. Stack 10. SOB 000111 i.sub.1 i.sub.0 0 &lt; i.sub.1 i.sub.0 &gt; 1 11. ROB 000110 i.sub.1 i.sub.0 0 &lt; i.sub.1 i.sub.0 &gt; .rarw. 0 ______________________________________
Where A represents the accumulator 6, r a designated register, M the memory device 9, PC the program counter 2, ST the stack 15 and O the output device 13. In the items of the instructions, the symbols, codes and the operation equations of the instructions are described in the order starting from the left sides. The LA instruction 1 belongs to the type (I) described above. The first four bits, that is 1010 correspond to an operation designator and the remaining four bits, that is r.sub.3 r.sub.2 r.sub.1 r.sub.0 correspond to an operand designator. The r.sub.3, r.sub.2, r.sub.1 and r.sub.0 are binary variables of which values are "0" or "1", and symbols "i" and "a" have the same meaning. With this instruction, according to the values (there are 16 values) of r.sub.3, r.sub.2, r.sub.1 and r.sub.0, the contents of the specified register are transferred to the accumulator 6. In this case, the source of the instruction is a register designated by r.sub.3 r.sub.2 r.sub.1 r.sub.0 whereas the destination is the accumulator 6. The registers designated as above described include H, L, I and M. When L register 11 is designated, a code r.sub.3 r.sub.2 r.sub.1 r.sub.0 is decoded by the instruction decoder 4 to generate the control signal SL which enebles gate circuit g.sub.8 to produce the output of the L register 11 on the bus 5. By only the code 1010 of the operation designator of this LA instruction, the destination can be identified as the accumulator 6 and this code is decoded by the instruction decoder 4 to generate the control signal DA which enables gate circuit g.sub.11 between the bus 5 and the accumulator 6 open so that the contents of the L register 11 are transferred to the accumulator 6. Where the designated register is the input device 12, the output thereof is decoded by the decoder 4 to produce control signal SI instead of SL so that the contents of the input device 12 would be transferred to the accumulator 6 as in the case of the L register. On the other hand, when the memory device 9 is designated, it becomes the source. In this case however, a word in the memory device 9 designated by the address of the contents of the H register and L register will be the object to be controlled.
ST instruction 2 is obtained by reversing the transfer objects of the LA instruction 1. wherein the source is fixed to the accumulator 6 and the destination comprises a register designated by r.sub.3 r.sub.2 r.sub.1 r.sub.0. The type of the instruction is (I) like instruction 1. The LAI instruction 3. also belongs to type (I). While this instruction resembles the LA instruction 1. it is different therefrom in that the source comprises immediate data which is included in the instruction code. In the case of this instruction, the instruction decoder 4 produces the control signal SIM which transfers one half of the contents of the instruction register 3, that is 4 bits to the bus 5 through gate circuit g.sub.9. The AAI instruction 4 also belongs to type (I) and, similar to LAI instruction 3, produces the immediate data on the bus 5. If differs, however, in that the output of ALU 7 is then transferred to the accumulator 6 via a gate circuit g.sub.12 under the control of the control signal DAA.
The ADD instruction 5 belongs to type (II) and all 8 bits of the code automatically determine to use the accumulator 6 and the memory device 9 as the source, and the accumulator 6 as the destination. The contents of the accumulator 6 and the memory device 9 are added together and the resulting sum is transferred to the accumulator 6. The AND instruction 6 belongs to the type (II) and the same source and the same destinations are designated as those of the ADD instruction 5. In this case, however, ALU 7 operates to produce logical products instead of sums. The JMP instruction 7 is a branch instruction having a two word length (16 bits) and belongs to the type (II). Under normal instructions of 1 through 6 the count value of the program counter 2 is incremented by 1. In this case, however, the program counter 2 itself is the object to be controlled. The source comprises a type of immediate data having 12 bits of a.sub.0 through a.sub.11 and the destination is the program counter 2. In this case, the program counter may also constitute another source and destination. The CALL instruction 8 performs the multiplex functions of executing the JMP instruction, and saving the contents of the program counter in the stack 15. This instruction is used to call a subroutine. The RTN instruction 9 is used to return from a subroutine to a main routine and also belongs to the type (II). In this case, the source comprises the stack 15 and the destination comprises the program counter 2.
The SOB instruction 10 is an input/output instruction and functions to set to state "1" only one bit among the 4 bits of the output device 13 which are designated by the code i.sub.1 i.sub.0. This instruction enables the operation of one bit unit with a data processing apparatus designed to process data having a length of 4 bits.
The ROB instruction 11 operates to reset 1 bit instead of setting 1 bit like the SOB instruction 10. In both instructions 10 and 11 only one specific bit of the output device 13 constitutes the destination. (Each one of the instructions 1 through 9 comprises 4 bits or 12 bits units.) Thus, these instructions belong to the type (I).
The instructions described above are only a portion of the entire instructions but they are typical ones. Instructions are classified into several groups according to the type of their operations, and in this example, instructions 1.about.3 comprise the transfer instructions, instructions 4.about.6 the arithmetical operation instructions, 7.about.9 the branch instructions and 10 and 11 the bit processing instructions. Furthermore, these instructions may be classified into types (I) and (II) mentioned above according to the manner of designating the operand. Thus, instructions LA 1, ST 2, LAI 3, AAI 4, SOB 10 and ROB 11 belong to type (I) whereas remaining instructions belong to type (II) meaning that the object to be operated is determined automatically. In the cases of instructions LAI 3., AAI 4., SOB 10. and ROB 11 the operands are limited although these instructions belong to group (I). Thus, in the case of instructions LAI and AAI, the sources are the immediate data, which does not designate a specific register. The instructions SOB and ROB control the respective bits of four bits in the output device. On the other hand, instructions LA 1 and ST 2 include valid operand designators. Where the operand designator is shortened to be less than 4 bits or where data processing apparatus employing instruction words having longer length is used, it is possible to determine the source and the destination as the operands which are determinable by the operand designator having a code that designates the respective two operands.
The most serious problem of the prior art data processing apparatus lies in that, due to the limit on the instruction word length, when the contents of the operation is special (that is the frequency of use decreases) the designated objects of operand to be operated should be limited. For example, in instructions such as LA 1 and ST 2 which are simple and used frequently for transfer, for example, it is possible to designate their operands, while in such instructions as ADD 5 and SOB 10 which are used for special operations and are used infrequently, different from simple transfer instruction, one must construct these instructions such that the operands are automatically determined and that no operand designator is contained in the entire instruction codes. Otherwise, instruction codes become deficient.
One method of solving this problem involves preparation of instructions having a length twice or three times of the fundamental word length of the instruction. To accomplish this, however, it is necessary to increase the bit number of the instruction register or to make more complicate the performance of the instruction decoder. This solution, however, accompanies such difficulties that even when the frequency of use of the instruction that executes the operation increases to some extent, (the frequency of use depends upon the field of application of the data processing apparatus and the programmer) one must use instructions having a twice or three times of length, thus, increasing the length of the program.